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dlx
The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design).
The DLX is essentially a cleaned up (and modernized) simplified Stanford MIPS CPU. The DLX has a simple 32-bit load/store architecture, somewhat unlike the modern MIPS architecture CPU. As the DLX was intended primarily for teaching purposes, the DLX design is widely used in university-level computer architecture courses.
There are two known "softcore" hardware implementations: ASPIDA and VAMP. The ASPIDA project resulted in a core with many nice features: it is open source, supports Wishbone, has an asynchronous design, supports multiple ISAs, and is ASIC proven. VAMP is a DLX-variant that was mathematically verified as part of Verisoft project. It was specified with PVS, implemented in Verilog, and runs on a Xilinx FPGA. A full stack from compiler to kernel to TCP/IP was built on it.
I have a NIB Winchester model 92 Delux Limited Edition. In 45 LC it is engraved and has gold inlayes on the receiver, and AAA walnut stock. 24 and 1/4” barrel
I need Y$2,000 out of it.
I have a very low use DLX Luxe X in polished pewter/polished black. It is just over a year old and has only been used a handful of times and has always been stored and taken care of when not being used. This is DLX's top model with a digital display and phone charger capabilities. This model...